TY - GEN
T1 - A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme
AU - Lo, Tien Yu
AU - Hung, Chung-Chih
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A continuous-time 4th-order equiripple linear phase G
m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.
AB - A continuous-time 4th-order equiripple linear phase G
m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=51349110036&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2007.4425717
DO - 10.1109/ASSCC.2007.4425717
M3 - Conference contribution
AN - SCOPUS:51349110036
SN - 1424413605
SN - 9781424413607
T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
SP - 408
EP - 411
BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Y2 - 12 November 2007 through 14 November 2007
ER -