A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme

Tien Yu Lo; Chung-Chih Hung

doi:10.1109/ASSCC.2007.4425717

A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme

Tien Yu Lo^*, Chung-Chih Hung

^*Corresponding author for this work

National Chiao Tung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

A continuous-time 4th-order equiripple linear phase G _m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	408-411
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425717
State	Published - 1 Dec 2007
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 12 Nov 2007 → 14 Nov 2007

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country	Korea, Republic of
City	Jeju
Period	12/11/07 → 14/11/07

Access to Document

10.1109/ASSCC.2007.4425717

Link to publication in Scopus

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Lo, T. Y., & Hung, C-C. (2007). A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 408-411). [4425717] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425717

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title = "A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme",

abstract = "A continuous-time 4th-order equiripple linear phase G m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.",

author = "Lo, {Tien Yu} and Chung-Chih Hung",

year = "2007",

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doi = "10.1109/ASSCC.2007.4425717",

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Lo, TY & Hung, C-C 2007, A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425717, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 408-411, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 12/11/07. https://doi.org/10.1109/ASSCC.2007.4425717

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N2 - A continuous-time 4th-order equiripple linear phase G m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.

AB - A continuous-time 4th-order equiripple linear phase G m-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-μm CMOS process, the chip occupies 1mm2 and consumes 175mW at a 1.5-V supply voltage.

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