A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, Tsung-Hsien Lin*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital-to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 ps(rms) integrated jitter (10 kHz to 30 MHz).

Original languageEnglish
Title of host publication2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
PublisherIEEE
Number of pages2
StatePublished - 2020
EventInternational Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu
Duration: 25 Apr 201627 Apr 2016

Publication series

NameInternational Symposium on VLSI Design Automation and Test
PublisherIEEE
ISSN (Print)2474-2724

Conference

ConferenceInternational Symposium on VLSI Design, Automation and Test (VLSI-DAT)
CityHsinchu
Period25/04/1627/04/16

Keywords

  • fractional output divider
  • phase rotating technique

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