A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network

Chih Lung Chen*, Sheng Jhan Wu, Hsie Chia Chang, Chen Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1∼100Mb/s with power consumption of 0.5∼9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.

Original languageEnglish
Title of host publication2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages229-232
Number of pages4
ISBN (Electronic)9781479940905
DOIs
StatePublished - 13 Jan 2015
Event2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan
Duration: 10 Nov 201412 Nov 2014

Publication series

Name2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
CountryTaiwan
CityKaohsiung
Period10/11/1412/11/14

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