A 0.9 pJ/b, Reference Clock Free, Delay-Based, All-Digital Coherent BPSK Demodulator

Chi Yi Lo, Hao Chiao Hong*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This letter proposes a novel reference clock free, delay-based coherent binary phase-shift keying (BPSK) demodulator suitable for biomedical devices which receive power and data through the same wireless link. The proposed BPSK demodulator mixes the BPSK input signal and its copy delayed by a half of the carrier period to generate a data flipping signal whose rising edges indicate when the phases of the BPSK signal flip. The data are then recovered by sampling the BPSK input signal using the derived data flipping signal. A phase selector recovers the coherent clock with a 50% duty cycle by selecting either the delayed BPSK input or its complement according to the recovered data. The open-loop operation of the proposed BPSK demodulator enables it to achieve a data rate as high as the carrier frequency. The all-digital implementation makes the demodulator compact, low power, and able to operate at 0.5 V. A test chip running with a 13.56-MHz carrier has been designed and fabricated. Measurement results show that at 0.9 V and a data rate of 13.56 Mb/s, the proposed demodulator only consumes 12.2 mu text{W} , corresponding to an FoM of 0.90 pJ/b. This FoM is at least 61 times better than those of the state-of-the-art designs.

Original languageEnglish
Article number9235385
Pages (from-to)498-501
Number of pages4
JournalIEEE Solid-State Circuits Letters
StatePublished - 2020


  • Binary phase-shift keying (BPSK)
  • coherent
  • delay-based
  • demodulator
  • wireless power transmission (WPT)

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