A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Chao Chang Chiu, Po Hsien Huang, Moris Lin, Ke-Horng Chen, Ying Hsi Lin, Tsung Yen Tsai, Chen Chih Huang, Chao Cheng Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
StatePublished - 17 Sep 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 12 Jun 201314 Jun 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period12/06/1314/06/13

Fingerprint Dive into the research topics of 'A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement'. Together they form a unique fingerprint.

Cite this