A 0.6 V resistance-locked loop embedded digital low dropout regulator in 40 nm CMOS with 80.5% power supply rejection improvement

Chao Chang Chiu*, Po Hsien Huang, Moris Lin, Ke-Horng Chen, Ying Hsi Lin, Tsung Yen Tsai, Chen Chao Cheng Lee

*Corresponding author for this work

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.

Original languageEnglish
Article number6879504
Pages (from-to)59-69
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number1
DOIs
StatePublished - 1 Jan 2015

Keywords

  • Current efficiency
  • digital low dropout (DLDO) regulator
  • resistance-locked loop (RLL)

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