A 0.6 v input CCM/DCM operating digital buck converter in 40 nm CMOS

Xin Zhang*, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

36 Scopus citations

Abstract

This paper presents a 0.6 V input, 0.3-0.55 V output buck converter in 40 nm CMOS, for low-voltage low-power wireless sensor network systems. A low power CCM/DCM controller of the buck converter enables automatic selection of DCM or CCM operation depending on load situation, therefore improving the power efficiency. A dual-mode-body-biased (DMBB) zero-crossing detector with both forward body bias mode and zero body bias mode is designed to enable DCM operation with both low supply voltage and normal supply voltage. An ultra-low-power hysteresis voltage detector is proposed for body bias modes selection. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50 μA to 10 mA. Thanks to the DCM operation, the efficiency at an output current of 10 μA is improved by 20% and 9%, with an output voltage of 0.35 V and 0.5 V, respectively.

Original languageEnglish
Article number6872611
Pages (from-to)2377-2386
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number11
DOIs
StatePublished - 1 Nov 2014

Keywords

  • Buck converter
  • DC-DC converter
  • forward body bias
  • low voltage
  • voltage detector

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