A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector

Xin Zhang, Yasuyuki Okuma, Po-Hung Chen, Koichi Ishida, Yoshikatsu Ryu, Kazumori Watanabe, Takayasu Sakurai, Makoto Takamiya

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias & zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages45-48
Number of pages4
DOIs
StatePublished - 1 Dec 2013
Event2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
Duration: 11 Nov 201313 Nov 2013

Publication series

NameProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
CountrySingapore
CitySingapore
Period11/11/1313/11/13

Fingerprint Dive into the research topics of 'A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector'. Together they form a unique fingerprint.

Cite this