A 0.6-7 Gbps, 1/7 rate, burst mode clock and data recovery circuit and demultiplexer

Yu Hsian Chen*, Wei-Zen Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A 1/7 rate, burst mode clock and data recovery circuit incorporating with demultiplexer is proposed. It covers 622 Mbps to 7 Gbps operation by selective-gating digitally controlled oscillator for phase synchronization and digital frequency-locked loop for frequency tracking. The latency for data recovery and 1:7 demultiplexing is less than 10 bit periods. Incorporating both CDR and demultiplexer, this chip consumes 1.5 mW, 6 mW, and 17 mW respectively at 622 Mbps, 2488Mbps, and 7Gbps operations. Implemented in a 90 nm CMOS technology, the chip area is 1.162 × 1.205 mm 2.

Original languageEnglish
Title of host publication2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
Pages531-534
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Montreal, QC, Canada
Duration: 17 Jun 201219 Jun 2012

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
CountryCanada
CityMontreal, QC
Period17/06/1219/06/12

Keywords

  • digital controlled oscillator
  • frequency locked loop
  • phase locked loop

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