A 0.5V 25Mpixels/s SVGA 30fps H.264 video decoder chip

Jia Wei Chen*, Pei Yao Chang, Keng Jui Chang, Tzu Yuan Kuo, Wei Han Hsu, Jinn Shyan Wang, Cheng An Chien, Hsiu Cheng Chang, Jiun-In Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A sub-threshold voltage, high throughput H.264 video decoder design is proposed for portable applications in this paper. To improve the performance for high throughput rate applications, the computational complexity in H.264 video decoding is optimized in the proposed design. To reduce complexity, both a shared adder-based hardware sharing scheme and an advanced data management scheme are presented. Moreover, to reduce power consumption, both a low area sub-threshold voltage SRAM and a high performance sub-threshold voltage CMOS circuit design scheme are presented. Exploiting all the design techniques, the proposed 90nm 0.5V 25Mpixels/s SVGA 30fps H.264 decoder outperforms the 65nm design at 0.5V through a 31 improvement in throughput.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages1-6
Number of pages6
DOIs
StatePublished - 1 Dec 2011
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
Duration: 12 Dec 201114 Dec 2011

Publication series

Name2011 International Symposium on Integrated Circuits, ISIC 2011

Conference

Conference2011 International Symposium on Integrated Circuits, ISIC 2011
CountrySingapore
CitySingaporeSingapore
Period12/12/1114/12/11

Keywords

  • CMOS digital integratd circuits
  • H.264/AVC
  • Low-power electronics
  • SRAM chip
  • Sub-threshold circuit design
  • Video codecs

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