A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM with Vtrip-Tracking Write-Assist

Shang Lin Wu, Kuang Yu Li, Po-Tsang Huang, Wei Hwang, Ming Hsien Tu, Sheng Chi Lung, Wei Sheng Peng, Huan Shun Huang, Kuen DI Lee, Yung Shin Kao, Ching Te Chuang

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-κ metal-gate (H κ MG) CMOS technology with macro area of 1058.22 × 374.76~ μm2. Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25°.

Original languageEnglish
Article number7885536
Pages (from-to)1791-1802
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number7
StatePublished - 1 Jul 2017


  • Low power
  • Low voltage
  • near-threshold
  • power-gating
  • static random access memory (SRAM)
  • write-assist

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