A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC

Sang Dhong, Richard Guo, Ming Zhang Kuo, Ping Lin Yang, Cheng Chung Lin, Kevin Huang, Min Jer Wang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and reduced dependence on the input rise-time and PVT variations were obtained using a new pulse generator. A pulse in the new generator starts when its input crosses the switching level of its input gate, unlike in the classic text-book-style pulse-generator. An 8 to 10% improvement in power, performance, and area (PPA) of a typical digital SOC is observed when a group of pulse latches is driven by a distributed clock regenerator (DCR). The DCR has the new pulse generator at its input stage and provides pulse clocks to the pulse latches. Experimental results in a 28-nm HKMG process closely match SPICE simulations.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
StatePublished - 4 Nov 2014
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: 15 Sep 201417 Sep 2014

Publication series

NameProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period15/09/1417/09/14

Keywords

  • Digital SOC
  • distributed clock regenerator
  • flipflops
  • pulse generator
  • pulse latch

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