This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tristate pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with V-DD down to 0.35 V (similar to 100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 mu W standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 mu W at 0.35 V. (C) 2016 Elsevier Ltd. All rights reserved.
- Low power; Subthreshold SRAM; Write-assist; 10T cell
- SENSE-AMPLIFIER; 8T SRAM; CELL; OPERATION; DESIGN; SCHEME