A 0.33-V, 500-kHz, 3.94-μW 40-nm 72-Kb 9T subthreshold SRAM with ripple bit-line structure and negative bit-line write-assist

Chien Yu Lu*, Ming Hsien Tu, Hao I. Yang, Ya Ping Wu, Huan Shun Huang, Yuh Jiun Lin, Kuen Di Lee, Yung Shin Kao, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 × 385μm2 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25°C. The measured total power consumption is 3.94 μW at 0.33 V, 500 kHz, and 25°C.

Original languageEnglish
Article number6423268
Pages (from-to)863-867
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number12
DOIs
StatePublished - 1 Dec 2012

Keywords

  • 9T SRAM cell
  • Negative bit-line (NBL)
  • ripple bit-line (RPBL)
  • subthreshold static random-access memory (SRAM)
  • ultra-low voltage

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