A 0.325 V, 600-kHz, 40-nm 72-kb 9T subthreshold SRAM with aligned boosted write wordline and negative write bitline write-assist

Chien Yu Lu, Ching Te Chuang, Shyh-Jye Jou, Ming Hsien Tu, Ya Ping Wu, Chung Ping Huang, Paul Sen Kan, Huan Shun Huang, Kuen Di Lee, Yung Shin Kao

Research output: Contribution to journalArticlepeer-review

19 Scopus citations

Abstract

This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of areaefficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for VDD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 °C. At 0.325 V and 25 °C, the chip operates at 600 kHz with 5.78 μW total power and 4.69 μW leakage power, offering 2× frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 °C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.

Original languageEnglish
Article number6812218
Pages (from-to)958-962
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number5
DOIs
StatePublished - 1 May 2015

Keywords

  • 9T static random access memory (SRAM)
  • boosted wordline
  • line-up write-assist (LUWA)
  • negative bitline
  • subthreshold
  • ultralow voltage.

Fingerprint Dive into the research topics of 'A 0.325 V, 600-kHz, 40-nm 72-kb 9T subthreshold SRAM with aligned boosted write wordline and negative write bitline write-assist'. Together they form a unique fingerprint.

Cite this