A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver

Cheng Chi Wong, Cheng Hao Tang, Ming Wei Lai, Yan Xiu Zheng, Chien Ching Lin, Hsie-Chia Chang, Chen Yi Lee, Yu T. Su

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 × 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages273-276
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
StatePublished - 1 Jan 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: 16 Sep 200719 Sep 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Conference

Conference29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period16/09/0719/09/07

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    Wong, C. C., Tang, C. H., Lai, M. W., Zheng, Y. X., Lin, C. C., Chang, H-C., Lee, C. Y., & Su, Y. T. (2007). A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 273-276). [4405731] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405731