A leading-edge 0.13 μm CMOS technology using 193nm lithography and Cu/low-k interconnect is described in this paper. High performance 80nm core devices use 17 Å nitrided oxide for 1.0-1.2V operation. These devices deliver unloaded 8.5ps gate delay @1.2V. This technology also supports general ASIC applications with 20 Å oxide for 1.2-1.5V operation and low-standby power applications with 26 Å for 1.5V operation, respectively. Dual gate oxides of 50 or 65 Å are also supported for 2.5V or 3.3V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high-density 1P3M 2.43 μm2 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 2000|
|Event||2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States|
Duration: 10 Dec 2000 → 13 Dec 2000