A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

Yao Chia Liu, Wei-Zen Chen, Mao Hsuan Chou, Tsung Hsien Tsai, Yen Wei Lee, Min Shueh Yuan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A 0.1-3 GHz, cell-based, fractional-N ADPLL with ΔΣ noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um × 240um.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467361460
DOIs
StatePublished - 7 Nov 2013
Event35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: 22 Sep 201325 Sep 2013

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

Conference35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
CountryUnited States
CitySan Jose, CA
Period22/09/1325/09/13

Keywords

  • fractional-N ADPLL
  • TDC
  • ΔΣ phase detector

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