A 0.1-0.3 v 40-123 fJ/bit/ch on-chip data link with ISI-suppressed bootstrapped repeaters

Yingchieh Ho*, Chau-Chin Su

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a ${-}V \rm DD to $2V \rm DD swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V $V \rm DD.

Original languageEnglish
Article number6165387
Pages (from-to)1242-1251
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue number5
DOIs
StatePublished - 1 May 2012

Keywords

  • Bootstrapped circuit
  • energy efficient
  • inter-symbol interference (ISI)
  • leakage current reduction low-power
  • low-voltage
  • sub-threshold circuit

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