9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

Wei Ling Chang; Chin-Chun Meng; Jin Siang Syu; Chia Ling Wang; Guo Wei Huang

doi:10.1109/SiRF.2014.6828507

9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

Wei Ling Chang, Chin-Chun Meng, Jin Siang Syu, Chia Ling Wang, Guo Wei Huang

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

Original language	English
Title of host publication	SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
Publisher	IEEE Computer Society
Pages	47-49
Number of pages	3
ISBN (Print)	9781479915231
DOIs	https://doi.org/10.1109/SiRF.2014.6828507
State	Published - 1 Jan 2014
Event	2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014 - Newport Beach, CA, United States Duration: 19 Jan 2014 → 23 Jan 2014

Publication series

Name	SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Conference

Conference	2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014
Country	United States
City	Newport Beach, CA
Period	19/01/14 → 23/01/14

Keywords

8-phase signal generator
Deep n-well vertical-NPN bipolar junction transistor
Direct-conversion receiver
Low flicker noise
Low power
Sub-harmonic mixer

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Chang, W. L., Meng, C-C., Syu, J. S., Wang, C. L., & Huang, G. W. (2014). 9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT. In SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (pp. 47-49). [6828507] (SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems). IEEE Computer Society. https://doi.org/10.1109/SiRF.2014.6828507

Chang, Wei Ling ; Meng, Chin-Chun ; Syu, Jin Siang ; Wang, Chia Ling ; Huang, Guo Wei. / 9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT. SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. IEEE Computer Society, 2014. pp. 47-49 (SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems).

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title = "9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT",

abstract = "A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.",

keywords = "8-phase signal generator, Deep n-well vertical-NPN bipolar junction transistor, Direct-conversion receiver, Low flicker noise, Low power, Sub-harmonic mixer",

author = "Chang, {Wei Ling} and Chin-Chun Meng and Syu, {Jin Siang} and Wang, {Chia Ling} and Huang, {Guo Wei}",

year = "2014",

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doi = "10.1109/SiRF.2014.6828507",

language = "English",

isbn = "9781479915231",

series = "SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems",

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Chang, WL, Meng, C-C, Syu, JS, Wang, CL & Huang, GW 2014, 9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT. in SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems., 6828507, SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, IEEE Computer Society, pp. 47-49, 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014, Newport Beach, CA, United States, 19/01/14. https://doi.org/10.1109/SiRF.2014.6828507

9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT. / Chang, Wei Ling; Meng, Chin-Chun; Syu, Jin Siang; Wang, Chia Ling; Huang, Guo Wei.

SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. IEEE Computer Society, 2014. p. 47-49 6828507 (SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chang, Wei Ling

AU - Meng, Chin-Chun

AU - Syu, Jin Siang

AU - Wang, Chia Ling

AU - Huang, Guo Wei

PY - 2014/1/1

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N2 - A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

AB - A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

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KW - Deep n-well vertical-NPN bipolar junction transistor

KW - Direct-conversion receiver

KW - Low flicker noise

KW - Low power

KW - Sub-harmonic mixer

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Chang WL, Meng C-C, Syu JS, Wang CL, Huang GW. 9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT. In SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. IEEE Computer Society. 2014. p. 47-49. 6828507. (SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems). https://doi.org/10.1109/SiRF.2014.6828507

9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

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Keywords

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