9.9-mA 5-6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

Wei Ling Chang, Chin-Chun Meng, Jin Siang Syu, Chia Ling Wang, Guo Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

Original languageEnglish
Title of host publicationSiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
PublisherIEEE Computer Society
Pages47-49
Number of pages3
ISBN (Print)9781479915231
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014 - Newport Beach, CA, United States
Duration: 19 Jan 201423 Jan 2014

Publication series

NameSiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Conference

Conference2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014
CountryUnited States
CityNewport Beach, CA
Period19/01/1423/01/14

Keywords

  • 8-phase signal generator
  • Deep n-well vertical-NPN bipolar junction transistor
  • Direct-conversion receiver
  • Low flicker noise
  • Low power
  • Sub-harmonic mixer

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