92% High efficiency and low current mismatch interleaving power factor correction controller with variable sampling slope and automatic loading detection techniques

Yi Ping Su, Chun Yen Chen, Chia Lung Ni, Yu Chai Kang, Yi Ting Chen, Jen Chieh Tsai, Ke-Horng Chen, Shih Ming Wang, Chao Chiun Liang, Chang An Ho, Tun Hao Yu

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-μm 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.

Original languageEnglish
Article number6412805
Pages (from-to)5159-5173
Number of pages15
JournalIEEE Transactions on Power Electronics
Volume28
Issue number11
DOIs
StatePublished - 20 May 2013

Keywords

  • Automatic loading detection (ALD)
  • dual nondeadtime variable sampling slope (DNVSS)
  • interleaving power factor correction (PFC)

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