8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Yi Wei Chiu*, Jihi Yu Lin, Ming Hsien Tu, Shyh-Jye Jou, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.

Original languageEnglish
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages169-174
Number of pages6
DOIs
StatePublished - 19 Sep 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: 1 Aug 20113 Aug 2011

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period1/08/113/08/11

Keywords

  • Data-Aware Write Operation
  • SRAM
  • Static Random Access Memory

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