A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.
|Number of pages||2|
|State||Published - 1 Jan 2001|
|Event||2001 IEEE International SOI Conference - Durango, CO, United States|
Duration: 1 Oct 2001 → 4 Oct 2001
|Conference||2001 IEEE International SOI Conference|
|Period||1/10/01 → 4/10/01|