80nm SOI CMOS parameter extraction for BSIMPD

K. Goto*, Pin Su, Y. Tagawa, T. Sugii, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations


A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.

Original languageEnglish
Number of pages2
StatePublished - 1 Jan 2001
Event2001 IEEE International SOI Conference - Durango, CO, United States
Duration: 1 Oct 20014 Oct 2001


Conference2001 IEEE International SOI Conference
CountryUnited States
CityDurango, CO

Fingerprint Dive into the research topics of '80nm SOI CMOS parameter extraction for BSIMPD'. Together they form a unique fingerprint.

  • Cite this

    Goto, K., Su, P., Tagawa, Y., Sugii, T., & Hu, C-M. (2001). 80nm SOI CMOS parameter extraction for BSIMPD. 55-56. Paper presented at 2001 IEEE International SOI Conference, Durango, CO, United States.