660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology

R. V. Joshi*, Wei Hwang, W. H. Henkels, S. Wilson, W. Rausch, G. Shahidi

*Corresponding author for this work

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

A register file and latch for bulk silicon technology was fabricated using SOI technology without any body contacts. The register file and latch function at frequencies higher than 660 MHz. The salient features are operability at low voltage, fully collision-free operation and minimum noise. A robust design is demonstrated with respect to input pulse width variation and skew margins. Charge sharing noise and noise due to leakage coupling and power supply variations are controlled using half latches on the dynamic nodes and property optimizing circuits and layouts.

Original languageEnglish
Pages131-132
Number of pages2
StatePublished - 1 Dec 1998
EventProceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA
Duration: 5 Oct 19988 Oct 1998

Conference

ConferenceProceedings of the 1998 IEEE International SOI Conference
CityStuart, FL, USA
Period5/10/988/10/98

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    Joshi, R. V., Hwang, W., Henkels, W. H., Wilson, S., Rausch, W., & Shahidi, G. (1998). 660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology. 131-132. Paper presented at Proceedings of the 1998 IEEE International SOI Conference, Stuart, FL, USA, .