65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

Samuel K.H. Fung*, H. T. Huang, S. M. Cheng, K. L. Cheng, S. W. Wang, Y. P. Wang, Y. Y. Yao, C. M. Chu, S. J. Yang, W. J. Liang, Y. K. Leung, C. C. Wu, C. Y. Lin, S. J. Chang, S. Y. Wu, C. F. Nieh, C. C. Chen, T. L. Lee, Y. Jin, S. C. ChenL. T. Lin, Y. H. Chiu, H. J. Tao, C. Y. Fu, S. M. Jang, K. F. Yu, C. H. Wang, T. C. Ong, Y. C. See, C. H. Diaz, M. S. Liang, Y. C. Sun

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

35 Scopus citations

Abstract

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1A and drive current is increased by 7%.

Original languageEnglish
Pages (from-to)92-93
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 2004
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 15 Jun 200417 Jun 2004

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