5nm-gate nanowire FinFET

Fu Liang Yang*, Di Hong Lee, Hou Yu Chen, Chang Yun Chang, Sheng Da Liu, Cheng Chuan Huang, Tang Xuan Chung, Hung Wei Chen, Chien Chao Huang, Yi Hsuan Liu, Chung Cheng Wu, Chi Chun Chen, Shih Chang Chen, Ying Tsung Chen, Ying Ho Chen, Chih Jian Chen, Bor Wen Chan, Peng Fu Hsu, Jyu Horng Shieh, Han Jan TaoYee Chia Yeo, Yiming Li, Jam Wem Lee, Pu Chen, Mong Song Liang, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

231 Scopus citations

Abstract

A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/"mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

Original languageEnglish
Pages (from-to)196-197
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Oct 2004
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 15 Jun 200417 Jun 2004

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