A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/"mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1 Oct 2004|
|Event||2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States|
Duration: 15 Jun 2004 → 17 Jun 2004