5.8 GHz low-flicker-noise CMOS direct-conversion receiver using deep-n-well vertical-NPN BJT

Yu Chih Hsiao*, Chin-Chun Meng, Jin Siang Syu, Chia Ling Wang, Shyh Chyi Wong, Guo Wei Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper demonstrates a 5.8 GHz low-power, low-flicker-noise direct-conversion receiver using deep-n-well vertical-NPN BJT based subharmonic Gilbert mixer. The deep-n-well vertical-NPN BJT is placed in the LO switching core of the bottom-level subharmonic mixer and the input transconductance stage of the subsequent IF VGA. As a result, the flicker noise corner is improved and the noise figure is 9.5 dB at IF=100 kHz. The maximum gain reaches 50 dB in the operated frequency. The total power consumption is 10 mW at 1.8 V supply voltage.

Original languageEnglish
Title of host publication2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
Pages467-470
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Montreal, QC, Canada
Duration: 17 Jun 201219 Jun 2012

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
CountryCanada
CityMontreal, QC
Period17/06/1219/06/12

Keywords

  • direct-conversion receiver
  • low power
  • subharmonic mixer
  • vertical-NPN bipolar junction transistor

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    Hsiao, Y. C., Meng, C-C., Syu, J. S., Wang, C. L., Wong, S. C., & Huang, G. W. (2012). 5.8 GHz low-flicker-noise CMOS direct-conversion receiver using deep-n-well vertical-NPN BJT. In 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers (pp. 467-470). [6242323] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2012.6242323