55-mW 300-MHz analog-digital converters using digital VLSI technology

P. Sutardja*, D. D. Tang, J. Altieri, L. E. Thon, G. Coleman, S. Subbanna, J. Y.C. Sun

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations


A very high speed analog-digital converter (ADC) has been designed and fabricated using a 3.6-V, 0.8-micron and a 2.5-V, 0.5-micron digital CMOS technology. This converter is intended for the evaluation of the potential of scaled CMOS technologies for analog application. This article describes the design issues and the performance of the ADC fabricated in two generations of CMOS.

Original languageEnglish
Number of pages2
StatePublished - 1995
EventProceedings of the 1995 IEEE Symposium on Low Power Electronics - San Jose, CA, USA
Duration: 9 Oct 199511 Oct 1995


ConferenceProceedings of the 1995 IEEE Symposium on Low Power Electronics
CitySan Jose, CA, USA

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