A very high speed analog-digital converter (ADC) has been designed and fabricated using a 3.6-V, 0.8-micron and a 2.5-V, 0.5-micron digital CMOS technology. This converter is intended for the evaluation of the potential of scaled CMOS technologies for analog application. This article describes the design issues and the performance of the ADC fabricated in two generations of CMOS.
|Number of pages||2|
|State||Published - 1995|
|Event||Proceedings of the 1995 IEEE Symposium on Low Power Electronics - San Jose, CA, USA|
Duration: 9 Oct 1995 → 11 Oct 1995
|Conference||Proceedings of the 1995 IEEE Symposium on Low Power Electronics|
|City||San Jose, CA, USA|
|Period||9/10/95 → 11/10/95|