500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch

W. H. Henkels*, Wei Hwang, R. V. Joshi

*Corresponding author for this work

Research output: Contribution to conferencePaper

9 Scopus citations

Abstract

A high performance multiport register file was designed and operated employing self-resetting CMOS(SRCMOS). The register file is tolerant to a very wide range of input pulsewidths but delivers tightly controlled outputs. In addition, SRCMOS dynamic-to-static conversion latch that enables the register file to be compatible with either dynamic or static dataflows is demonstrated.

Original languageEnglish
Pages41-42
Number of pages2
DOIs
StatePublished - 1 Dec 1997
EventProceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 12 Jun 199714 Jun 1997

Conference

ConferenceProceedings of the 1997 Symposium on VLSI Circuits
CityKyoto, Jpn
Period12/06/9714/06/97

Cite this

Henkels, W. H., Hwang, W., & Joshi, R. V. (1997). 500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch. 41-42. Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, . https://doi.org/10.1109/VLSIC.1997.623792