5 Gbps serial link transmitter with pre-emphasis

Chih Hsien Lin, Chung Hong Wang, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

A high-speed serial link that achieves Gbps performance has the advantage of low cost and is thus set to become popular. In this paper, we implement the high-speed data serial link transceiver and demonstrate the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18 μm 1P6M 1.8 V CMOS process. The performance of the transceiver can reach 5 Gbps over the 10-meter long cable.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages795-800
Number of pages6
ISBN (Electronic)0780376595
DOIs
StatePublished - 1 Jan 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 21 Jan 200324 Jan 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period21/01/0324/01/03

Fingerprint Dive into the research topics of '5 Gbps serial link transmitter with pre-emphasis'. Together they form a unique fingerprint.

Cite this