The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1 Oct 2004|
|Event||2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States|
Duration: 15 Jun 2004 → 17 Jun 2004