45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Fu Liang Yang*, Cheng Chuan Huang, Chien Chao Huang, Tang Xuan Chung, Hou Yu Chen, Chang Yun Chang, Hung Wei Chen, Di Hong Lee, Sheng Da Liu, Kuang Hsin Chen, Cheng Kuo Wen, Shui Ming Cheng, Chang Ta Yang, Li Wei Kung, Chiu Lien Lee, Yu Jun Chou, Fu Jye Liang, Lin Hung Shiu, Jan Wen You, King Chang ShuBin Chang Chang, Jaw Jung Shin, Chun Kuang Chen, Tsai Sheng Gau, Ping Wei Wang, Bor Wen Chan, Peng Fu Hsu, Jyu Horng Shieh, Samuel K.H. Fung, Carlos H. Diaz, Chii Ming M. Wu, Yee Chaung See, Bum J. Lin, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference article

17 Scopus citations

Abstract

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

Original languageEnglish
Pages (from-to)8-9
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Oct 2004
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 15 Jun 200417 Jun 2004

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