40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

Fan Ta Chen, Jen Ming Wu, Mau-Chung Chang

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.

Original languageEnglish
Article number7070853
Pages (from-to)1042-1051
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number4
DOIs
StatePublished - 1 Apr 2015

Keywords

  • CMOS
  • Current-mode logic
  • DEMUX
  • MUX
  • SerDes
  • inductive peaking
  • latch
  • transformer-coupled technique

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