3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor

Chen Han Chou, Chung Chun Hsu, Steve S. Chung, Chao Hsin Chien

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

We propose a novel device structure, namely T-FinFET, for sub-14nm MOSFET with using lighter anti punch through (APT) implant. According to 3D TCAD simulation, the T-FinFET is found to posses many advantages over the normal FinFET, such as better short channel effect (SCE) and drain induced barrier lowering (DIBL), having smaller S/D capacitance and junction leakage and fewer masks. Compared to gate-all-around (GAA) structure, the T-FinFET also has compatible electrical performance. All these features are obtained by depositing a self-aligned (SA) oxide after recessing the Si fin in the S/D region. It can be applied to Ge and III-V MOSFETs for suppressing the SCEs and S/D leakage, arising from higher permittivity and lower band gap than Si.

Original languageEnglish
Title of host publication2015 Silicon Nanoelectronics Workshop, SNW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863485389
StatePublished - 24 Sep 2015
EventSilicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
Duration: 14 Jun 201515 Jun 2015

Publication series

Name2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
CountryJapan
CityKyoto
Period14/06/1515/06/15

Keywords

  • Doping
  • FinFETs
  • Implants
  • Logic gates
  • Process control
  • Solid modeling
  • Three-dimensional displays

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    Chou, C. H., Hsu, C. C., Chung, S. S., & Chien, C. H. (2015). 3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor. In 2015 Silicon Nanoelectronics Workshop, SNW 2015 [7275311] (2015 Silicon Nanoelectronics Workshop, SNW 2015). Institute of Electrical and Electronics Engineers Inc..