3D Ta/TaO x /TiO 2 /Ti synaptic array and linearity tuning of weight update for hardware neural network applications

I. Ting Wang, Chih Cheng Chang, Li Wen Chiu, Teyuh Chou, Tuo-Hung Hou

Research output: Contribution to journalArticlepeer-review

62 Scopus citations

Abstract

The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaO x /TiO 2 /Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.

Original languageEnglish
Article number365204
JournalNanotechnology
Volume27
Issue number36
DOIs
StatePublished - 1 Aug 2016

Keywords

  • RRAM
  • electronic synapse
  • hardware neural network
  • three dimensional

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