3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

K. Tsutsui*, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. OmuraH. Ohashi, H. Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
EditorsYajie Qin, Zhiliang Hong, Ting-Ao Tang
PublisherIEEE Computer Society
Pages1137-1140
Number of pages4
ISBN (Electronic)9781509066247
DOIs
StatePublished - 1 Jul 2017
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: 25 Oct 201728 Oct 2017

Publication series

NameProceedings of International Conference on ASIC
Volume2017-October
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period25/10/1728/10/17

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