3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

Y. D. Lin, Y. T. Tang, S. S. Sheu, T. H. Hou, W. C. Lo, M. H. Lee, M. F. Chang, Y. C. King, C. J. Lin, H. Y. Lee, P. C. Yeh, H. Y. Yang, P. S. Yeh, C. Y. Wang, J. W. Su, S. H. Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrOx FRAM technology that shows a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at VDD of 4V.

Original languageEnglish
Title of host publication2019 IEEE International Electron Devices Meeting, IEDM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728140315
DOIs
StatePublished - Dec 2019
Event65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
Duration: 7 Dec 201911 Dec 2019

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2019-December
ISSN (Print)0163-1918

Conference

Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
CountryUnited States
CitySan Francisco
Period7/12/1911/12/19

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