3D integration for VLSI systems

Chuan Seng Tan*, Kuan Neng Chen, Steven Koester

*Corresponding author for this work

Research output: Book/ReportBookpeer-review

3 Scopus citations

Abstract

Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV. There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.

Original languageEnglish
PublisherPan Stanford Publishing Pte. Ltd.
Number of pages377
ISBN (Electronic)9789814303828
ISBN (Print)9789814303811
DOIs
StatePublished - 19 Apr 2016

Fingerprint Dive into the research topics of '3D integration for VLSI systems'. Together they form a unique fingerprint.

Cite this