3D GOI CMOSFETs with novel IrO 2(Hf) dual gates and high-κ dielectric on 1P6M-0.18μm-CMOS

D. S. Yu*, Albert Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. Zhu, M. F. Li, W. J. Yoo, S. P. McAlister, D. L. Kwong

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

53 Scopus citations


For the first time, we demonstrate 3D integration of self-aligned IrO 2(Hf)/LaAlO 3/GOI CMOSFETs above 0.18 μm Si CMOSFETs. At EOT=1.4nm, the novel IrO 2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO 3/Si devices have high electron and hole mobilities of 203 and 67 cm 2/Vs. On the 3D structure the LaAlO 3/ GOI shows even higher 389 and 234 cm 2/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.

Original languageEnglish
Pages (from-to)181-184
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - 1 Dec 2004
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: 13 Dec 200415 Dec 2004

Fingerprint Dive into the research topics of '3D GOI CMOSFETs with novel IrO <sub>2</sub>(Hf) dual gates and high-κ dielectric on 1P6M-0.18μm-CMOS'. Together they form a unique fingerprint.

Cite this