3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °c sequential layered integration

Yu Chung Lien*, Jia Min Shieh, Wen Hsien Huang, Wei Shang Hsieh, Cheng Hui Tu, Chieh Wang, Chang Hong Shen, Tung Huan Chou, Min Cheng Chen, Jung Y. Huang, Ci Ling Pan, Yin-Chieh Lai, Chen-Ming Hu, Fu Liang Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm 2 /V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 o C new-type metal-ion (Eu +3 )-mediated atomic-polar-structured (Eu +3 -APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed data-storage application era.

Original languageEnglish
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
DOIs
StatePublished - 1 Dec 2012
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: 10 Dec 201213 Dec 2012

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period10/12/1213/12/12

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