3D 65nm CMOS with 320°C microwave dopant activation

Yao Jen Lee*, Yu Lun Lu, Fu Kuo Hsueh, Kuo Chin Huang, Chia Chen Wan, Tz Yen Cheng, Ming Hung Han, Jeff M. Kowalski, Jeff E. Kowalski, Dawei Heh, Hsi Ta Chuang, Yi-Ming Li, Tien-Sheng Chao, Ching Yi Wu, Fu Liang Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Original languageEnglish
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
DOIs
StatePublished - 1 Dec 2009
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: 7 Dec 20099 Dec 2009

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2009 International Electron Devices Meeting, IEDM 2009
CountryUnited States
CityBaltimore, MD
Period7/12/099/12/09

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