3.5ns CMOS 64K ECL RAM at 77°K

S. E. Schuster*, T. I. Chappell, B. A. Chappell, J. W. Allan, J. Y.C. Sun, S. P. Klepner, R. L. Franch, P. F. Greier, P. J. Restle

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations

Abstract

A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.

Original languageEnglish
Pages17-18
Number of pages2
StatePublished - 1988
Event1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
Duration: 22 Aug 198824 Aug 1988

Conference

Conference1988 Symposium on VLSI Circuits - Digest of Technical Papers
CityTokyo, Japan
Period22/08/8824/08/88

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