35nm CMOS FinFETs

Fu Liang Yang*, Haur Ywh Chen, Fang Cheng Chen, Yi Lin Chan, Kuo Nan Yang, Chih Jian Chen, Hun Jan Tao, Yang Kyu Choi, Mong Song Liang, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

45 Scopus citations

Abstract

We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 Å gate oxide thickness, the transistors give drive currents of 1240 μA/μm for NFET and 500 μA/μm for PFET at an off current of 200 nA/μm. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.

Original languageEnglish
Pages104-105
Number of pages2
StatePublished - 1 Jan 2002
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: 11 Jun 200213 Jun 2002

Conference

Conference2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period11/06/0213/06/02

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