350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

Hiroyuki Hara*, Yasuhiro Sugimoto, Makoto Noda, Tetsu Nagamatsu, Yoshinori Watanabe, Hiroshi Iwai, Yoichirou Niitsu, Gen Sasaki, Kenji Maeguchi

*Corresponding author for this work

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.

Original languageEnglish
Pages (from-to)8.5/1-4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - May 1989
EventProceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA
Duration: 15 May 198918 May 1989

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    Hara, H., Sugimoto, Y., Noda, M., Nagamatsu, T., Watanabe, Y., Iwai, H., Niitsu, Y., Sasaki, G., & Maeguchi, K. (1989). 350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure. Proceedings of the Custom Integrated Circuits Conference, 8.5/1-4.