35 GHz/35 psec ECL pnp technology

J. Warnock*, P. F. Lu, J. D. Cressler, K. A. Jenkins, J. Y.C. Sun

*Corresponding author for this work

Research output: Contribution to journalConference article

14 Scopus citations


The authors report how self-aligned pnp devices with basewidths close to 50 nm have been fabricated using a preamorphizing Ge implant prior to the As base implant. They investigated the sensitivity of pnp performance to collector epi thickness, base width and the energy of the base implant, culminating in the achievement of devices with fT as high as 38 GHz. ECL (emitter coupled logic) ring oscillators built with these pnp devices have delays as small as 35 ps per stage, demonstrating that the device parasitics have been successfully minimized. Both the fT of 38 GHz and the 35 ps ECL delay represent new records for pnp devices, showing a performance level comparable to that of current high-performance npn technologies.

Original languageEnglish
Pages (from-to)301-304
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1990
Event1990 International Electron Devices Meeting - San Francisco, CA, USA
Duration: 9 Dec 199012 Dec 1990

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