30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D

Yang Kyu Choi*, Yoo Chan Jeon, Pushkar Ranade, Hideki Takeuchi, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

20 Scopus citations

Abstract

MOSFETs with selectively deposited Ge raised S/D implemented in 8nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650C, 20sec). Devices with gate length down to 30nm are obtained with 8nm UTB and show excellent short-channel behavior.

Original languageEnglish
Pages23-24
Number of pages2
StatePublished - 1 Jan 2000
Event58th Device Research Conference (58th DRC) - Denver, CO, USA
Duration: 19 Jun 200021 Jun 2000

Conference

Conference58th Device Research Conference (58th DRC)
CityDenver, CO, USA
Period19/06/0021/06/00

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