MOSFETs with selectively deposited Ge raised S/D implemented in 8nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650C, 20sec). Devices with gate length down to 30nm are obtained with 8nm UTB and show excellent short-channel behavior.
|Number of pages||2|
|State||Published - 1 Jan 2000|
|Event||58th Device Research Conference (58th DRC) - Denver, CO, USA|
Duration: 19 Jun 2000 → 21 Jun 2000
|Conference||58th Device Research Conference (58th DRC)|
|City||Denver, CO, USA|
|Period||19/06/00 → 21/06/00|