This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-μm-diameter/50-μm-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-μm diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
- Backside-via-last TSV
- three-dimensional heterogeneous integration