28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications

Yi Chun Wu, Po-Tsang Huang, Shang Lin Wu, Sheng Chi Lung, Wei Chang Wang, Wei Hwang, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-low-power FIFO memory is designed and implemented using bit-interleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256×16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538642603
DOIs
StatePublished - 5 Jun 2018
Event2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
Duration: 16 Apr 201819 Apr 2018

Publication series

Name2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
CountryTaiwan
CityHsinchu
Period16/04/1819/04/18

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