27Gbit/s AIGaAs/GaAs HBT 1:2 regenerating demultiplexer IC

K. Runge, J. L. Gimlett, R. B. Nubling, K. C. Wang, Mau-Chung Chang, R. L. Pierson, P. M. Asbeck

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


An experimental 27 Gbit/s 1:2 regenerating demultiplexer IC based on AlGaAs/GaAs HBTs has been implemented, which features an input sensitivity of 55 mV peak to peak and a phase marpn of 270° at the SONET STS-192 rate of 9·95 Gbit/s. The circuit was fabricated in a high current gain baseline HBT technology, and occupies an area of 115 × 1 mm2.

Original languageEnglish
Pages (from-to)2389-2391
Number of pages3
JournalElectronics Letters
Issue number25
StatePublished - 5 Dec 1991


  • Demultiplexers
  • Digital communications
  • Integrated circuits

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