Abstract
An experimental 27 Gbit/s 1:2 regenerating demultiplexer IC based on AlGaAs/GaAs HBTs has been implemented, which features an input sensitivity of 55 mV peak to peak and a phase marpn of 270° at the SONET STS-192 rate of 9·95 Gbit/s. The circuit was fabricated in a high current gain baseline HBT technology, and occupies an area of 115 × 1 mm2.
Original language | English |
---|---|
Pages (from-to) | 2389-2391 |
Number of pages | 3 |
Journal | Electronics Letters |
Volume | 27 |
Issue number | 25 |
DOIs | |
State | Published - 5 Dec 1991 |
Keywords
- Demultiplexers
- Digital communications
- Integrated circuits