2.4 GHz divide-by-256-271 single-ended frequency divider in standard 0.35-μm CMOS technology

Sheng Che Tseng*, Chin-Chun Meng, Shao Yu Li, Jen Yi Su, Guo Wei Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by-4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2×0.7 mm2.

Original languageEnglish
Title of host publicationAPMC 2005
Subtitle of host publicationAsia-Pacific Microwave Conference Proceedings 2005
DOIs
StatePublished - 1 Dec 2005
EventAPMC 2005: Asia-Pacific Microwave Conference 2005 - Suzhou, China
Duration: 4 Dec 20057 Dec 2005

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume2

Conference

ConferenceAPMC 2005: Asia-Pacific Microwave Conference 2005
CountryChina
CitySuzhou
Period4/12/057/12/05

Keywords

  • CMOS
  • Current mode logic
  • Divide-by-4/5
  • Prescaler
  • Single-ended

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    Tseng, S. C., Meng, C-C., Li, S. Y., Su, J. Y., & Huang, G. W. (2005). 2.4 GHz divide-by-256-271 single-ended frequency divider in standard 0.35-μm CMOS technology. In APMC 2005: Asia-Pacific Microwave Conference Proceedings 2005 [1606402] (Asia-Pacific Microwave Conference Proceedings, APMC; Vol. 2). https://doi.org/10.1109/APMC.2005.1606402