An unique time-interleaved dual injection locking scheme has been devised to enable ultra high-speed and low-power frequency division with extended frequency locking range. To prove the concept, two frequency dividers (or prescalers) have been realized in 65nm digital CMOS: one divides continuously from 158GHz to 195GHz (or 21% locking range) with input signal < 0dBm and the other divides from 181GHz to 208GHz (or 14% locking range) with input signal < -1dBm. Both prescalers consume < 2.5mW at 1V supply and contribute negligible phase noise. These test results set the highest F.O.M. (2721 and 2188 GHz2/mW, respectively) for prescalers implemented in any semiconductor technology up to this date, which in both cases is almost 10 times higher than that of prior arts.