200GHz CMOS prescalers with extended dividing range via time-interleaved dual injection locking

Qun Jane Gu, Heng Yu Jian, Zhiwei Xu, Yi Cheng Wu, Mau-Chung Chang, Yves Baeyens, Young Kai Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

An unique time-interleaved dual injection locking scheme has been devised to enable ultra high-speed and low-power frequency division with extended frequency locking range. To prove the concept, two frequency dividers (or prescalers) have been realized in 65nm digital CMOS: one divides continuously from 158GHz to 195GHz (or 21% locking range) with input signal < 0dBm and the other divides from 181GHz to 208GHz (or 14% locking range) with input signal < -1dBm. Both prescalers consume < 2.5mW at 1V supply and contribute negligible phase noise. These test results set the highest F.O.M. (2721 and 2188 GHz2/mW, respectively) for prescalers implemented in any semiconductor technology up to this date, which in both cases is almost 10 times higher than that of prior arts.

Original languageEnglish
Title of host publicationProceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
Pages69-72
Number of pages4
DOIs
StatePublished - 16 Jul 2010
Event2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010 - Anaheim, CA, United States
Duration: 23 May 201025 May 2010

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
CountryUnited States
CityAnaheim, CA
Period23/05/1025/05/10

Keywords

  • Figure-of-merit
  • High speed prescaler/frequency divider
  • Time-interleaved dual injection locking

Fingerprint Dive into the research topics of '200GHz CMOS prescalers with extended dividing range via time-interleaved dual injection locking'. Together they form a unique fingerprint.

Cite this